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Electrical Engineering

  • In this course, students will get familiar with the fundamental principles behind electronic/ photonic properties of organic materials, and will learn how those principles can be built into real-world devices such as organic light emitting diodes (OLED), solar cells, and field-effect transistors. Upon completion, students will be able to build a solid foundation that they can later apply to real engineering problems in related areas. Being targeted to EE students, this course will NOT require students any extensive knowledge of chemistry.

    TA: Tae-Wook Koh & Hyunsu Cho (T.5483)

  • To introduce research activities of KAIST EECS faculties and future technical challenges and of electronics engineering.

  • Modern VLSI designs, which can be found in most electronic devices such as a cell phone, are made of literally "very large" number of logic gates (a million for instance). Obviously, human designers cannot handle this level of scale; the only way is to allow designers to use a "language" such as Verilog so that they can write down the "function" they want in their circuits rather than deal with the connection of a million of logic gates. The remaining jobs (transform that function into a connection of logic gates, and ultimately into their physical connection, which can be manufactured as a "chip") are then done by "computer", in other words by "software programs".

    These software programs are collectively called "CAD tools" or "EDA (Electronic Design Automation) tools". These tools are not of push-button, i.e. there are many parameters or options designers may set depending on their designs, they may iterate a series of tools many many times, they quite often make another program (called a script) to set a sequence each tool needs to go through, but most importantly there is no universal tool that can design everything. Depending on a new design and a new technology, new design requirements and challenges emerge, which call for a new set of tools or refinement on existing tools.

    This course has three components: logic synthesis, physical synthesis, and high-level synthesis. The basic question in logic synthesis is how to derive "best" netlist (a connection of logic gates) from a designer specified function. We will address two- and multi-level logic minimization, sequential synthesis, technology mapping, and timing analysis. Physical synthesis represents the next step: input is a netlist and output is a layout. We will address such topics as floorplanning, placement, and routing. High-level synthesis tries to increase the level of designers' abstraction even higher: up to "algorithm". The question here is how to derive a "structural description" from "algorithm", which is done by steps called scheduling, allocation, and control synthesis.

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